Pentium M to get 64-bit support, Extreme EditionSossaman, wossaman, wossaname?By Charlie Demerjian: Tuesday 08 March 2005, 11:57A LOT OF PM NEWS floating around IDF last week. Let's get you caught up on the newer bits. First, there is a new socket, but we are not sure whether it is for Yonah, Sossaman or both. Either way, it has 480 pins, supports dual CPUs, and has a tag under the socket that looks like the picture below.What more is there to say? How about Napa64 and a PM-EE? The PM-EE is more interesting of the two, it is a Yonah with the lid blown off the TDP. If you can have really good performance with the current 31w, imagine what you could do with 60? If, and I do mean IF, the project gets green lighted, expect it in late Q1/06 at ~2 apwwd bins above the current Yonah clock. That currently is 2.5GHz, and Yonah is currently capable of multipliers that will bring it above 3.0GHz, so it should be an pretty easy SKU to bring out.Socket 480 tag.Napa64 is a tad more iffy than the PM-EE right now. The theory is this, you have a great platform in Napa, so how do you compete with AMD if you don't have 64 bits? The EE is a start, but it is reactionary. You take the true next gen chip, Merom, and put it out early.The problem with this approach is the chipset is a little behind the chip, so you twiddle the Yonah chipset enough to make it work. That is the basis of the Napa64 philosophy, and I can say there are boards up and running now in preparation for this. There won't be Meroms to plug into it for another two quarters or so, but it will be a good thing anyway. If AMD pulls out all the stops with the dual core Turion like the paranoid™ Intel is expecting, it will have a bunch of good counters.Now, there are two open questions with this. If the Nehalem cores have CSI, how the #*(&$# do they fit in the PM socket? The short story is that Merom and Conroe were pulled in to counter AMD, and something had to give. That something was CSI, and it was cut out until the refresh of the Nehalem cores around the time that Tukwila is set to come out. Tukwila is going to be late, look for a late 2007 launch, maybe slipping into early 2008, and it will probably take CSI with it.The other thing the socket brings us to is memory controllers. How can you bring the memory controller on board if you don't have the pins? Simply put, you don't, you keep it on the NB. It seems Intel values the flexibility of an external controller over the reduced latency for consumer level applications. While I can't say I agree, I do see there are several good reason to do so. If it goes deeper than that, can someone explain it to me please?So, in summary, 480, 60w EE, Napa64 with two sockets, Merom without CSI and memory controllers, and Tukwila late. Got it? µ
