First off, since when does L2 cache have _anything_ to do withperformance? If that was the case, then Intel's 2-4MB L2 cache on theP4 processors should have been be smacking the A64 silly!Secondly, people _forget_ that AMD processors have *4*TIMES* the L1cache of Intel processors! L1 is far, far more of a consideration --especially in how AMD's non-exclusive cache design works compared toIntel's exclusive cache design.I.e., In an Intel processor, it _must_ load data into L1 cache beforethe registers. In an AMD processor, it can _directly_ load from L2cache into registers. With a _small_ L1 cache, the Intel really hurtsfrom this.People forget about AMD's L1 cache _advantage_. It's a major reason whyAMD is able to "keep up" with Intel's fabrication lead. In fact, Inteloften has to "waste transistors" in adding more L2 to "make up" for itssmall L1.> > Blah, its already testing out poorly.No, not "poorly." AMD HyperTransport (A64/T64) processors do _smack_Intel NetBurst (P4) processors silly.> > I'll wait for the Core 2 Duo for the laptop.Intel has finally _chucked_ the _inefficient_ Netburst architecture.The reason why Netburst existed is because it was a "stop gap" design tomerely bridge from IA-32 P6/Pentium Pro (ignoring the original Pentium,it had too many bugs) to IA-64 Itanium. So it did a quick, 18 month"refit" by extending the pipes and doing _no_ redesign.Why? 7 years ago, Intel thought we would all be Itanium by now.Unfortunately, that wasn't reality (don't get me started on IA-64 --it's a "computer science" "paper ideal" that almost _every_ single oneof us "electrical engineers" said would _fail_, _utterly_, and itdid ;-) .So Intel _finally_ decided to _really_ rev the P6/Pentium Pro with afull 36-48 month re-design circa 2002-2003. That is now the Corearchitecture. It's very efficient, just like the P6 was -- totally theopposite of the Netburst (P4).Understand that this is Intel's _first_ IA-32[e] redesign since thePentium Pro of 1994. So now, with the introduction of the Core design,Intel has a 5-6 year lead on AMD -- in addition to their 12-18 monthfabrication lead.AMD's last redesign was the Athlon (yes, 32-bit) in 1999. TheA64/Opteron (including Turion64) is the _same_ architecture. Theoriginal Athlon was actually a 40-bit platform -- based on the 64-bitDigital Alpha 21x64 -- and easily extended to 64-bit registers. That'swhy AMD could do it without a major redesign.The _only_ major advantage that AMD has over Intel is in the 2+ wayspace, especially 4+ way. It had already built a non-shared, _truly_switched platform interconnect in the Athlon based on the Digital EV6.They merely moved it from a switch crossbar to a partial mesh. In fact,as I understand it, AMD's multicore is the EV6 Xbar internally, meaningthey could easily go to 13-core with_out_ any redesign (EV6 is 16-wayminus 3, 2 for the dual DDR channels plus 1 for HyperTransport).The switched/mesh design _forces_ AMD to put an I/O MMU on the CPU.This took a _years_ for AMD to mature, which it did in the originalAthlon MP (yes, 32-bit). That's because of memory coherency for I/O --with a "shared bus" Intel just relies on the chipset. With AMD, it hasto maintain _full_ I/O coherency on _each_ processor. Now that hasturned into a _major_ advantage -- as Opterons maintain memory mappedI/O affinity to _each_ processor.The result is that Opteron scales much, much better than Intel Xeon"shared bus" design. Even it's forthcoming, split bus is still not thesame. Although it will allow Xeon to scale a little better incombination with IBM's X3 architecture (long story).But it's clear that with Intel's return to the _efficient_ Pentium Probase in the Core processor, and the _end_ of Netburst (P4), Intel isback in the lead as far as ALU performance. Combined with theirproliferation of "lossy math" SSE (whereas AMD does SSE with its full,3-issue FPU for greater precision -- great for scientific/engineeringapps, but who cares about video/games?), Intel is in a pretty position.> > My wife has a Turion chip in her laptop, and it runs well. However, the> > cache (or lack thereof) on the Turion X2 is a dealbreaker for me.Huh? Why does the L2 cache matter?For _me_, the L1 cache size in Intel's processors and the requirementthat _all_ L2 go through that _tiny_ L1 is the "deal breaker." ;->Seriously now, buying something for L2 cache size is like saying you'renot going to buy a car with a smaller gas tank. Yeah, it can't feed theengine and go as far without stopping for gas than a car with a biggergas tank.But the L2 cache has _nothing_ to do with the L1 cache like the gas tankhas _nothing_ to do with the displacement of the engine. Seriously!Yeah, my car with a smaller gas tank will "stall" before the larger oneunless I get gas -- but with 4x the engine displacement like L1 cache, I_could_ be much farther down the road when I do stop! ;->Com'mon Kyle! You've been listening to marketing. ;->Buy a Core 2 Duo because of the _performance_. The L2 cache has_nothing_ to do with that. There's no more proof in that than themassive and often _useless_ L2 cache sizes of the Netburst (P4)architecture. You could put 32MB of L2 cache on a Netburst and it_still_ would _not_ beat an AMD A64-based design.Again, the Core 2 Duo is a return to and an improvement over theoriginal P6 (Pentium Pro) core. That's why it's very, very competitivewith AMD MHz for MHz -- _unlike_ Intel Netburst (P4). And because Intelhas a 12-18 month lead in fabrication over AMD (because fabs cost_billions_ of dollars), Intel can offer higher frequencies for the sameseries/price.Hence why Core 2 Duo wins. It has _little_ to do with L2 cache size,especially given AMD's _superior_ L1 cache feed directly to theregisters.