HyperTransport 3.0 , multicore heaven .

[TrinireturnofGamez]

http://www.dailytech.com/article.aspx?newsid=1943

HT 3.0 will now transmit up to one meter at the maximum specified clock speed with no signal loss.  Effectively, HyperTransport can be used to connect from one machine to another in the correct conditions. DailyTech previously spoke to PathScale, a company focused on making high-speed InfiniBand interconnects. According to PathScale, AMD's HyperTransport interconnect provides greater overall bandwidth and scalability over anything else currently available.

 

   Hyper Transport 3.0 clocks at 2.6ghz , providing 22 GB/s of bandwidth ,   not that any one processor will need so much loving , rather it is designed for many cored systems , Also the 1 metre limit  allows for systems to connect to one another at blazing speeds  , fast enough even to  tie 3 or 4 seperate motherboards, their processors, RAM and hard drives  into ONE efficient virtual machine ( 22GB/S versus 1gigabit ethernet)  ... Imagine  running  any application on a  system with  32 gigs of ram, 8 quad core processors and  16 hard drives in RAID ?
     AMD should be able to beat back  intel soon as they can implement these new technologies  in  late 2006/ early 2007 ,its already impossible for an 8 core Xeon to out do an 8 core Opteron due to the superior nature of AMD's multiple Hyper Transport links for each processor  , Veruses each xeon fighting over one bus ....
http://anandtech.com/IT/showdoc.aspx?i=2745&p=4  < check anandtech before a biscuit tells you otherwise .

[Spazosaurus]

One word...OMGWTFINTELTAKEDATANDCOOLITPWNERSHIP!!!!!!

[W1nTry]

This is nothing we didn't expect, however take into account HT was created by an emporium (AMD being 1 of the many pioneer's of said group) and is an open standard. So technically IF and I do mean IFF (IFF==If and ONLY IF) they really wanted to they could liscense HT3, draft it to the Xeon (Woodcrest) and they'd be back in business. Not to mention take into accont the kind of performance Intel is getting off of a overcrowded FSB FAR less for a bandwidth DREAM interface. True they'd have to eat MOUNTAINS of pride, but hey it would put them way in the lead I figure.

[Spazosaurus]

So Intel could pick this up just as easily then?

[W1nTry]

Well technically yes, but it's not THAT easy to replace your FSB architecture with something else. It's an integral part of your chip.

[Spazosaurus]

Hmmmm so this is another improvement that we'll see on the AM2 platform. I imagine that only a small number of the higher end cpu's will sport this bus. Can you imagine if something similar is done with the PCI-E bus? Mega SLI iwmc.

[TrinireturnofGamez]

 Opteron are supposed to support this very early on ie. early 2007 ,  it will trickle down to the rest of AMD's processors later , the difference is high end opteron systems will get MULTIPLE HT links , as much as 4 ! ....
   Yea if intel implements Core and Hyper Transport to , and an integrated memory controller right now  they would  make it hard for AMD to catch up.
      Conroe performance drops to only 2-5% faster than an equally clocked AMD64 when doing heavy multi tasking and all it's cache is used up due to it needing to have to access the RAM on its sucky , high latency bus ....
  Intel is scheduled to begin using integrated memory controllers in 2008 .. but by then AMD is supposed to have implemented other schemes for performance , like high density shared L3 and L2 cache  , integrated PCI- X controllers etc....
     

[W1nTry]

Trini are you sure about PCI-X? and not PCIe??? you have ALWAYS made the mistake of using PCI-X to mean PCIe. THey are VERY different, so get it right. I read it was PCIe not -X. This is only the 5th+ time i've pointed this particular point out.

[Czar]

You're quite correct win....they're gonna integrate the PCIe controller...an integrated PCI-X controller would only help the Opteron family...since the server chips are the only ones that use PCI-X.