New CPU from VIA (not picosized this time)

[W1nTry]

Some new stuff, sounds good, always been a fan of the little x86 company that could...

VIA releases a brand new core

Shows off CN/Isaiah

By Charlie Demerjian: Thursday, 24 January 2008, 9:50 AM

VIA TODAY BROKE cover on it's newest CPU code named Isaiah, also known as the near mythical CN. If you were expecting another lacklustre, mildly-warmed-over C3/5/7 you will be very disappointed, this one is all new from the ground up.

Via might not have been all that groundbreaking of late, and its CPUs are far from knocking a Yorktown off the top of the charts, but this one has all the right bullet points to get the firm back in the game.

It's a fully out of order superscalar CPU built on a 65nm process with 1M of L2 cache. It will run up to 2GHz with a 25W TDP, and in general delivers twice the performance of the C7 at the same power.

CN/Isaiah die plot

Via would not talk die sizes, but based on the package size (22 * 22mm), we would estimate it at about 65mm2 or roughly twice what the C7 is. This may sound like a massive bit of bloat, but the transistor count went from ~25M in the C7 to 94M in the CN, much of which is in the cache. For those of you who are interested, it is fabbed by Fujitsu, but they didn't say that officially.

Moving on down the bullet point line, they have full 64-bit instructions and on top of it, hardware acceleration of VMs, Intel compatible, not AMD. There are also a ton of other 'modern' must-have features like SSE1/2/3, but more on that as we delve a bit deeper.

To start out with, as we mentioned, the C7 was in order, the CN is out of order, and this is the major contributor to the 2x+ clock for clock speed increase. In addition to that, the CN is speculative, IE it can guess at what is coming and take limited actions based on what it expects to do next. It is also superscalar meaning it can do multiple things in parallel, in this case it can decode 3 x86 instructions per clock and retire up to three fused instructions per clock.

Yes, you read that right, it has the equivalent of Intel's vaunted macro and micro op fusion so that it can take x86 instructions and group them together when necessary in order to only generate one internal op from two x86 ops. That is the macro part, the micro is the same thing with the decoded instructions. The example most often given is a compare followed by a jump fused into a single instruction as a macro op fusion.

This all means that the CN has a bit of throughput, decoding 3 ops per clock, generating 3 fused micro ops, issue up to seven of them per clock, and retire three fused micro ops. By any count it is a fair chunk of code flying through the machine.

To feed the beast, you start out with 64K of 16 way set associative L1 cache and 1M of 16 way L2. The L2 is exclusive and anything entering it must be evicted from the L1 first. On top of this, you have full prefetch units, memory disambiguation similar to the Core Number Numeral, and store-to-load forwarding. Basically, it has all the goodies on paper, a complete clean sweep of the bullet point checkboxes.

To execute the code, there are seven units, a strangely coincidental number considering the 7 micro ops that it can execute per clock, almost as if they were tied together. These correspond to two integer, a load, a store data, store address, media execute and multiply. Most of these should be self explanatory, but the media instruction is a FP multiply, divide, add, or SIMD instruction. It can also do more complex ops like square roots.

One detail that Via seems to have paid a lot of attention to is instruction latency, especially FP latency. It can issue 4 FP adds and 4 FP multiplies per clock, and has a 2 cycle latency for adds, 3 and 4 for SP and DP mults respectively. This is faster than Core Number Numerals by at least a clock, and they also claim that SSEx instructions almost all execute in a single clock.

More new features are found in power states, all modern CPUs have a C4 low power state, and many have a rather nebulous C5/6 state, common definitions of which seem to be a little hard to come by. In any case, CN seems to line up with Penryn pretty well here.

The Via defined C5 state is like C4 but is flushes the cache and powers it down to prevent leakage. The next step down, C6, saves state to internal ram and then literally powers down the CPU. State is kept by external voltages leaving about 1M transistors, basically the RAM, powered on. If you do the math, this saves about 98% of the leakage power lost by the CPU.

Another nifty feature is called adaptive P-State control. The chip has some smarts as far as power management goes, if it is running hot, it can lower the voltage, and conversely, if it is running cool, it can bump up the clocks. By far the coolest part is called Adaptive Thermal Limit, as far as I can tell a unique CN feature. What this does is allow you to set a temp and it will throttle based on that maximum temp, allowing you to customize the CPU for the chassis, device or possibly the weather.

CN also has a the same crypto features as the older chips, Via calls this padlock, and most of the security crowd I talk to thinks very highly of it. The one new feature that CN has is something called Secure Execution Mode where encrypted instructions are streamed into the CPU and only decoded on die making it next to impossible to peek at what is being done. Quite interesting, but I can not see any end user good coming from this, but the content MAFIAA might just love it.

On the outside, it has the same V4 bus as the C7 and comes in the same 22 * 22mm package. In fact, it is pin compatible with the C7 should you choose to desolder your older part and put in a new one. Via also promises to have an 11 * 11mm package on the market soon, but all the ones we saw today were the older 22mm packages.

Looking out a bit farther, there will be dual core versions, and multiple sockets are a capability, up to 4 with CN. I really doubt we will see that in products soon, but the capability is there to do shared bus dual dies like Intel as well as shared L2 dual cores should the market need it.

Fanless 1.2GHz CN

There were three demonstration units out at Via/Centaur HQ today, a 1.2GHz fanless model running 720p video, a 1.4GHz running a 1080p Blu-Ray movie, and a 2GHz model running various games. With an NV 7950 on board, it ran Crysis acceptably but not at frame rates that would make a Skulltrail blush.

CN-based devices

There were also a bunch of sub-notebooks on display based on the familiar Packard-Bell/Nanobook design. Additionally, they had a little cube called the Mtube, a wimax enabled MID that is smaller than a pack of cigarettes.

It is pretty clear where Via is taking the CN, small efficient low cost PCs, small notebooks, and devices below that. They have a roadmap for continuous tweaks, upgrades and additions for the next several years, and the CN appears to be a good starting point. We will know for sure by the end of Q2 when it is slated for release, until then, it looks good. µ

Sorry i'm a bit lazy to put the pics in, so you can check it out here: http://www.theinquirer.net/gb/inquirer/news/2008/01/24/via-releases-brand-core